1. Field of the Invention
The present invention generally relates to semiconductor devices and semiconductor systems, and particularly relates to a MCP (multi-chip package) device which has one package containing a memory chip and a logic chip.
2. Description of the Related Art
When connecting a logic device with a memory device, generally, a common bus is used for connecting between the devices. FIG. 1A is an illustrative drawing of a related-art configuration in which a logic device is connected to a memory device via a common bus. As shown in FIG. 1A, a common bus 503 connects between a logic device 501 and a memory device 502, and performs data transfer therebetween.
An increase in data-transfer speed between the logic device 501 and the memory device 502 is required for enhancing a data processing performance. In order to achieve this, the number of signal lines of the bus 503 may be incremented in FIG. 1A, and/or a frequency of a clock signal may be increased with regard to data transfer. An increase in the number of bus signal lines is not particularly desirable in that the bus signal lines end up occupying a larger area in a chip, and, also, power consumption will be increased.
An attempt to raise the frequency of a data-transfer clock signal is generally hampered by a limit of signal-transfer capacities of the bus signal lines and/or by a limit of data-input/output speed of each device. Difficulties will be encountered, therefore, when one tries to increase the frequency beyond these limits.
One-chip LSIs in which a logic device and a memory device are implemented on the same chip offers a solution to the above-identified problems. FIG. 1B is an illustrative drawing showing a one-chip LSI which integrates a logic device and a memory device into one chip. As shown in FIG. 1B, a one-chip LSI 510 includes a memory unit 511 and a logic unit 512 implemented thereon. Since the memory unit 511 and the logic unit 512 are connected to each other via internal signal lines inside the chip, a high-speed data transfer can be achieved.
Manufacturing of one-chip LSIs, however, requires efforts to develop a new process technology for creating the memory unit 511 and the logic unit 512 via the same process, thereby incurring an increased cost. Further, when the memory unit 511 and the logic unit 512 are manufactured by a common process, a resulting performance of the chip is likely to be less than those which can be expected when each unit is manufactured by a dedicated separate process.
As described above, when a common bus is used for connecting a logic device and a memory device, difficulties are encountered in boosting data-transfer speed between the two devices. On the other hand, one-chip LSIs in which a logic unit and a memory unit are implemented on the same chip have drawbacks in an increased cost and a reduced performance.
Accordingly, there is a need for a semiconductor system which can achieve a data-transfer speed compatible to that of one-chip LSIs at a low cost.